ADT7463
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45
Table 71. XOR TREE TEST ENABLE REGISTER (POWERON DEFAULT = 0X00) (Note 1)
Register Address
R/W
Description
0x6F
R/W
XNOR Tree Test Enable
Bit
Name
Description
<0>
XEN
If the XEN bit is set to 1, the device enters the XOR tree test mode.
Clearing the bit removes the device from the XOR test mode.
<7:1>
RES
Unused. Do not write to these bits.
1. This register becomes readonly when the Configuration Register 1 Lock bit is set to 1. Further attempts to write to this register have no effect.
Table 72. REMOTE 1 TEMPERATURE OFFSET REGISTER (POWERON DEFAULT = 0X00) (Note 1)
Register Address
R/W
Description
0x70
R/W
Remote 1 Temperature Offset
<7:0>
R/W
Allows a twos complement offset value to be automatically added to or subtracted from the
Remote 1 Temperature reading. This is to compensate for any inherent system offsets such as
PCB trace resistance. LSB value = 0.25癈.
1. This register becomes readonly when the Configuration Register 1 Lock bit is set to 1. Further attempts to write to this register have no effect.
Table 73. LOCAL TEMPERATURE OFFSET REGISTER (POWERON DEFAULT = 0X00) (Note 1)
Register Address
R/W
Description
0x71
R/W
Local Temperature Offset
<7:0>
R/W
Allows a twos complement offset value to be automatically added to or subtracted from the local
temperature reading. LSB value = 0.25癈.
1. This register becomes readonly when the Configuration Register 1 Lock bit is set to 1. Further attempts to write to this register have no effect.
Table 74. REMOTE 2 TEMPERATURE OFFSET REGISTER (POWERON DEFAULT = 0X00) (Note 1)
Register Address
R/W
Description
0x72
R/W
Remote 2 Temperature Offset
<7:0>
R/W
Allows a twos complement offset value to be automatically added to or subtracted from the
Remote 2 temperature reading. This is to compensate for any inherent system offsets such as
PCB trace resistance. LSB value = 0.25癈.
1. This register becomes readonly when the Configuration Register 1 Lock bit is set to 1. Further attempts to write to this register have no effect.
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